1. Field of the Invention
The present invention relates to testing of an integrated circuit, or xe2x80x9cchipxe2x80x9d, and more particularly, to an apparatus and method for parallel testing of a plurality of functional blocks of a single chip, each of which generates the same output signal for a given common input signal.
2. Description of the Related Art
As system-on-a-chip (SOC) design becomes increasingly widespread, it is more common to place a plurality of redundant cores, or functional blocks, on a single chip. In such circuits, a plurality of digital cores each having the same function, a plurality of memory cores each of the same size, or a plurality of analog cores may coexist on the same integrated circuit.
During testing of such circuits, it is determined whether each of the resident redundant functional blocks generates the same output for a given input provided to all blocks. In order to simultaneously test the functional blocks, an external test stimulus is provided to each functional block input, and the resulting response is sensed at each functional block output. Test stimulus can be simultaneously provided to all functional blocks via a single input pin and distributed, or xe2x80x9cfanned-outxe2x80x9d to each functional block. However, an output pin for each individual functional block is required to simultaneously transfer the test response of each functional block external to the chip. Increasing the output pin count for testing purposes is highly undesirable in circuit design practice.
For reducing the total number of output pins, a pin sharing technique and a multiple input signature register (MISR) technique have been suggested.
In the conventional pin sharing technique, the several outputs of the functional blocks are provided to a multiplexer which selectively transfers one among the functional block outputs to the test output pin. Thus, the number of test output pins can be reduced. However, this technique does not allow for the functional blocks to be tested in parallel, i.e., tested at the same time. In view of this, chip testing according to this technique is time consuming, and further, chip verification cannot be performed under real-time conditions.
Further, according to the conventional MISR method, the number of output pins can be reduced; however, a defective part response can be misrecognized as a non-defective response, leading to inaccurate test results.
It is an object of the present invention to provide an apparatus for the parallel testing of a plurality of functional blocks residing on a single chip, each of which generates a similar output for a given input, in real time, using only a restricted number of output pins.
It is another object of the present invention to provide a method for the parallel testing of a plurality of functional blocks residing on a single chip.
To achieve the first object of the present invention, there is provided an apparatus for the parallel testing of an integrated circuit, the integrated circuit including a plurality of functional blocks, each of which, in response to a common stimulus, generates like output signals. The apparatus comprises a comparator, a transmitter, and a failure discriminator. The comparator compares the levels of the output signals from each of the functional blocks, and outputs a comparison result. A transmitter externally transmits one of the output signals in response to the comparison result. A failure discriminator compares the transmitted output signal level to a predetermined target output signal level, and if similar, transmits a positive test result signal.
The failure discriminator preferably further transmits a negative test result signal when the transmitted output signal level and target output signal level are different. The transmitter preferably transmits one of the output signals when the comparator determines the output signal levels to be the same and transmits a defect signal when the comparator determines the output signal levels to be different.
The functional blocks may comprise circuit types consisting of analog circuits, digital circuits, and memory banks. Each of the functional blocks may digitally process the stimulus to each generate an N-bit output signal. In this case, the signal output to the comparator from each functional block comprises an arbitrary signal bit of the N-bit output signal. The comparator may comprise N-comparators, each for comparing the levels of like bits of the output signals.
To achieve the second object of the present invention, there is provided a method for the parallel testing of an integrated circuit, the integrated circuit including a plurality of functional blocks, each of which, in response to a common stimulus, generates like output signals. It is first determined whether the levels of the output signals from each of the functional blocks are the same. If the output signals are the same, one of the output signals is transmitted external to the integrated circuit. If the output signals are not all the same, none of the output signals are transmitted external to the integrated circuit. Next, it is determined whether the level of transmitted output signal is the same as a predetermined target output signal level. If the level of the output signal is substantially the same as the target level, the integrated circuit is deemed non-defective; otherwise, if all output signals are not the same, or if the level of the transmitted output signal is not the same as the target level, the integrated circuit is deemed defective.